In fabrication of a stack structure of copper interconnect layers in a semiconductor device through, for example, a dual damascene process, copper is embedded in a depression on an interlayer insulation film, copper residues are removed by chemical mechanical polishing (CMP), and a barrier layer is formed on a surface of a copper interconnect exposed on the interlayer insulation film and on a surface of the interlayer insulation film. The barrier layer serves to prevent diffusion of copper into the interlayer insulation film, and is composed of, for example, a SiCN layer formed of a compound of silicon (Si), carbon (C) and nitrogen (N), a SiC layer formed of a compound of silicon and carbon, or a SiN layer formed of a compound of silicon and nitrogen. In addition, the barrier layer also serves as an etching stopper in the case of stacking an interlayer insulation film of an upper layer on a surface of a substrate, followed by etching to form a depression on the interlayer insulation film.
Further, since the barrier layer has poor adhesion with copper, in order to improve reliability of interconnects through improvement of cohesion between the barrier layer and the copper interconnects, a method of forming a thin film between the barrier layer and the copper interconnects is known in the art. For example, a thin film of CoWP (cobalt-tungsten-phosphorous) or CoWB (cobalt-tungsten-boron) may be formed by electroless plating. However, CoWP or CoWB has high conductivity and provides a high possibility of short circuit between interconnects when attached to a surface of the interlayer insulation film. Moreover, the interlayer insulation film is likely to suffer from damage or metal contamination during the cleaning of the substrate after electroless plating. Further, a process of forming a manganese layer on copper interconnects is known. However, some processes of forming copper interconnects do not allow deposition of manganese oxide on a surface of the copper interconnect.